The Vyoma Way
Smartest way to verification sign-off using Vyoma's Verification-as-a-service platform
Adopt Pre-developed RISC-V VIPs
Re-use Vyoma's RISC-V VIPs following the UVM (Universal Verification Methodology) framework for providing a scalable, simulation-based verification environment.
Adapt Python-based Vyoma's IPs
Transform the UVM methodology towards using the next-generation language (Python) and Vyoma's rich IP ecosystem.
Accelerate with Vyoma's DevSecOps
Faster bug detection, verification sign-off through rapid simulation productivity using the cloud without compromising verification quality.
Offerings
RISC-V Processor Verification IPs
Supporting RV[32|64]IMAFDCSUN
RISC-V is an open ISA standard targeting next generation semiconductor market. Vyoma provides ready-to-deploy test generators, checkers and ISA coverage collectors for delivering high quality RISC-V products. Roadmap: Vector, Hypervisor and Multi-core
Python Based Verification IPs
Supporting Python UVM Environment
Leverage the rich open CoCoTb based Python ecosystem for rapid verification environment development. Vyoma offers Python-based verification support facilitating improved productivity.
Vyoma's UpTickPro
Verification-as-a-Service Platform for RISC-V Processor and Systems Verification
Next Generation cloud based infrastructure for highly scalable and re-useable Verification environment.
Frequently Asked Questions
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Is Vyoma's Python based verification a drop-in replacement for the existing verification frameworks?
No, it is not a drop-in replacement and it is not intended to be. With our expertise in design verification, we provide lighter, more scalable verification environments catering to increasing domain-specific complexities of digital design verification.
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Are we looking at migrating all the working verification environment to Vyoma's way?
It does not make sense to redo an already existing stable verification environment unless we add new verification strategies to the existing framework. Vyoma's way is towards developing environments from scratch for newly developed designs (such as RISC-V based) or for innovation in a verification environment where there is a need and scope to bring in ML (machine learning) based feedback for improved verification productivity.
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Will it support all language features of the existing verification methodology?
To answer the question from a different point of view, the Python-based framework will guarantee the same verification quality as that of the existing verification methodology. Vyoma's effort is to provide that seamless confidence towards the verification sign-off and facilitate the know-how for rapid environment development and maintenance. In other words, it will not support the features that no longer serve the verification needs. However, it will always retain the simulation environment features that enable constraint random test generation, highly re-usable verification environment, and coverage definition.
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How is Python based verification relevant for RISC-V designs and why should I adapt the Vyoma way?!
The RISC-V ISA and its design implementation are huge success stories for community collaboration. Vyoma strives to enable this collaboration amongst industry and academia for processor verification through this Python based verification approach. For more information on Vyoma's way and whether this approach will benefit you, feel free to contact us. We will be more than thrilled to understand and resolve your verification needs.
Contact Us
Email:
info@vyomasystems.com
Address:
B Block, 5th, IITM RESEARCH PARK, B5-01, Kanagam Rd, Kanagam, Tharamani, Chennai, Tamil Nadu 600113