Adopt, Adapt and Accelerate the Vyoma way

Embrace the next generation design verification for improved productivity

The Vyoma Way

Smartest way to verification sign-off using Vyoma's Verification-as-a-service platform

Adopt

Retain the time tested UVM (Universal Verification Methodology) framework for providing a scalable, simulation-based verification environment.

Adapt

Transform the UVM methodology towards using the next-generation language (Python) and leveraging the state-of-the-art cloud compute available.

Accelerate

Faster bug detection, verification sign-off through rapid simulation productivity without compromising verification quality.

Offerings

RISC-V Processor Verification

In person/remote training and consulting services

RISC-V is an open ISA standard targeting next generation semiconductor market. Vyoma caters to building the expertise for verifying these highly configurable RISC-V designs and aiding the time-to-market for RISC-V based products.

Python Based Verification

In person/remote training and consulting services

Leverage the rich open Python ecosystem for rapid verification environment development. Vyoma offers training and consulting to adopt Python-based verification facilitating improved productivity.

VaaS Platform

Coming Soon!

Verification-as-a-Service platform leveraging next generation verification methodology and compute infrastructure.

Offerings Brochure

  • All
  • RISC-V Verification
  • Python Verification
  • VaaS Support

RISC-V Verification Training

VaaS

Python Verification Training

Frequently Asked Questions

  • No, it is not a drop-in replacement and it is not intended to be. With our expertise in design verification, we provide lighter, more scalable verification environments catering to increasing domain-specific complexities of digital design verification.

  • It does not make sense to redo an already existing stable verification environment unless we add new verification strategies to the existing framework. Vyoma's way is towards developing environments from scratch for newly developed designs (such as RISC-V based) or for innovation in a verification environment where there is a need and scope to bring in ML (machine learning) based feedback for improved verification productivity.

  • To answer the question from a different point of view, the Python-based framework will guarantee the same verification quality as that of the existing verification methodology. Vyoma's effort is to provide that seamless confidence towards the verification sign-off and facilitate the know-how for rapid environment development and maintenance. In other words, it will not support the features that no longer serve the verification needs. However, it will always retain the simulation environment features that enable constraint random test generation, highly re-usable verification environment, and coverage definition.

  • The RISC-V ISA and its design implementation are huge success stories for community collaboration. Vyoma strives to enable this collaboration amongst industry and academia for processor verification through this Python based verification approach. For more information on Vyoma's way and whether this approach will benefit you, feel free to contact us. We will be more than thrilled to understand and resolve your verification needs.

They trusted us

Vyoma's verification frameworks are validated with the SHAKTI Class of RISC-V processors

Contact Us

Address:

1B, Dev Apartments, Thiruveedi Amman Koil St., Dr. Seethapathy Nagar, Velachery, Chennai 600042